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Da ta She et, V1 .2, De c. 2 00 2
TC1765
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2002-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2002.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta She et, V1 .2, De c. 2 00 2
TC1765
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
TC1765 Data Sheet Preliminary Revision History: Previous Version: Page 58, 59 60 61 62 69 80 83 All 22 61 62 66 69 74 75 81 82
2002-12 V1.1, 2002-10, V1.0, 2002-05
V1.2
Subjects (major changes since last revision) Overshoot conditions (notes 2) and 3)) for digital supply voltages added Class A pins: input low voltage VILmin (CMOS) improved; pull-up/pull-down current spec corrected and completed; Class A pins: pull-up/pull-down current spec corrected and completed; Note 7) inserted Note 3) added to "Sum of IDDS"
Changes from V1.1 to V1.2
t30min corrected
Package outlines updated (no more "Preliminary" in drawing) In general: Data Sheet status changed from "Advance Information" to "Preliminary" The SSC RXFIFO and TXFIFO are 4-stage FIFOs (not 8-stage) Input hysteresis corrected Footnote 10) added Footnote 8): word "numeric" added Missing power supply currents now specified Last paragraph modified because of Figure 29 correction Figure 29 corrected and improved
Changes from V1.0 to V1.1
t55 added (min. value) and corrected (max. value) t61min and t62min corrected
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
Preliminary
32-Bit Single-Chip Microcontroller TriCore Family
TC1765
* High Performance 32-bit TriCore CPU with 4-Stage Pipeline - 25 ns Instruction Cycle Time at 40 MHz CPU/System Clock * Dual Issue super-scalar implementation - Instruction triple issue * Circular Buffer and bit-reverse addressing modes for DSP algorithms * Flexible multi-master interrupt system * Very fast interrupt response time * Hardware controlled context switch for task switch and interrupts * 48 Kbytes of on-chip SRAM for data and time critical code * 8-channel DMA Controller for FPI Bus transactions * Built-in calibration support * On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional units * External Bus Interface Unit (EBU) with dedicated pins used for - Communication with external data memories and peripheral units - Instruction fetches from external Burst Flash program memories * On-Chip Peripheral Units - General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex I/O management - Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters - Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baudrate generator, parity, framing and overrun error detection - Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable data length and shift direction - TwinCAN Module with two interconnected CAN nodes for high efficiency data handling via FIFO buffering and gateway data transfer - Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit resolution and 24 analog inputs - Watchdog Timer and System Timer * 77 digital general purpose I/O lines and one 24-bit analog port * On-chip Debug Support * Power Management System * Clock Generation Unit with PLL * Two derivatives with upward compatible pin configuration - TC1765N - TC1765T (with additional 16-bit OCDS Level 2 trace port) * Ambient temperature under bias: -40 C to +125 C * P-LBGA-260 package
Data Sheet 1 V1.2, 2002-12
TC1765
Preliminary Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. The TC1765 is available with the following ordering code: Type Ordering Code Package Description
SAK-TC1765N-L40EB Q67121-C2326
P-LBGA-260 32-Bit Single-Chip Microcontroller 40 MHz, -40 C to +125 C P-LBGA-260 32-Bit Single-Chip Microcontroller 40 MHz, -40 C to +125 C (with OCDS2 trace port)
SAK-TC1765T-L40EB
Q67121-C2348
Data Sheet
2
V1.2, 2002-12
Figure 1
DMU (D ata M em ory U nit) 128 m ax . 40 M H z Trac e & OCDS Interrupt 32 64 32 K B S R A M TriC ore C PU PM U (Program M em ory U nit)
TP
Analog Input Connection
Port 4
Data Sheet
V DDRAM
8 K B B oot R O M 16 K B S cratch P ad R A M 1 K B Instruc tion C ache
Preliminary
Block Diagram
V DDSBRAM
TraceP ort
16
16
V DDO SC V SSO SC
C P U C LK OSC
TC1765 Block Diagram
F P I STM BCU PLL 32 32 F P I B us 24 5 SSC 0 Twin CAN 10 DMA C ontroller B u s SC U P ow erW atchdogR es et S ys . C ntrl. X TA L1 X TA L2 E C IN ECOUT D ata [31:0] A ddress [23:0] EB U (E x ternal B us U nit) C hip S elect EBU C ontrol 5 2 2 3 P ort 0 16
M C B04989
(TC 1765T only ) OCDS 3 C ontrol C ontrol 5 5 J TA G IO A nalog 10 P ow er S upply
JT A G & C erberus
16
3
G PTA GPTU A SC 1 A SC 0 SSC 1 3 P ort 2 16 16 5 P ort 1 P ort 5 16 16 2 3 7 5 2 3 4
ADC1
A N 24 [23:0]
16
ADC0
8
8
3
16
2
10
V DDP V DD
23
P ort 3
V SS
16
V1.2, 2002-12
TC1765
TC1765
Preliminary Logic Symbol
T E S TM O D E G e ne ra l C o ntro l HDRST PORST NMI BYPASS X T A L1 X T A L2 O scilla tor 5 10
D [3 1:0 ] A [23 :0] C h ip S e le ct C o ntro l E C IN ECOUT A lte rn ate F u nc tio ns P o rt 0 16 -B it P o rt 1 16 -B it P o rt 2 16 -B it G PTA G PTU / ASC0 / SSC0 / CAN / ADC0 / ADC1 E xte rna l B u s Inte rfa ce
V DDOSC V SSOSC
CPUCLK TRST TCK TDI TDO TM S OCDSE B R K IN BRKO UT T P [15 :0]
(TC 1 7 6 5 T o n ly)
JT A G / O C D S
TC1765T TC1765N
P o rt 3 16 -B it P o rt 4 8-B it P o rt 5 5-B it A N [2 3:0 ] G PTA / CFG ASC1 SSC1 ADC A n alog Inp uts
V DDP
D ig ita l C irc uitry P ow er S u p ply
5 10
V DD 23 V SS V DDRAM V DDSBRAM
V AREF0 V AG ND0 V DDA0 V S S A0 V AREF1 V AG ND1 V DDA1 V S S A1
M C A 04973
A D C 0 A n alog P o w e r S u pp ly
A D C A n alog P ow e r S up ply
V DDM V SSM
A D C 1 A n alog P o w e r S u pp ly
Figure 2
Data Sheet
TC1765 Logic Symbol
4 V1.2, 2002-12
TC1765
Preliminary Pin Configuration
1 A B C D E F G H J K L M N P R T U V AN 17 AN 19
2 AN 16 AN 18 AN 20 AN 23
3 AN 8 AN 11 AN 10 AN 12 AN 15 AN 22
4
5 AN 7 AN 5 AN 6 AN 3
6 AN 4 AN 2
7 AN 0
8
9
10 P 0.0 P 0.9
11 P 0.4 P 0.15 P 5.3
12 P 0.5
13 P 0 .8 P 5 .1 P 4 .1 P 4 .5
14
15
16 P 5.4
17 P 4.2
18 P 3 .11 A B C D E F G H J K L M N P R T U V
V SSM V DDM
AN 9 AN 13 AN 14 AN 21
V A R E F0 V D D A 0
P 0.2 P 0.7
P 0.10 P 0.14 P 5.2 P 3.12 P 4.0 P 4 .3 P 4 .6 P 3.13 P 3 .4 P 3 .1
V SSA0
V DDP
P 4.7 P 5.0
P 3 .1 5 P 3 .1 4 P 3 .10 P 4.4 P 3.9 P 3.7 P 3.5 P 3.8 P 3.6 P 3.2 P 2 .15
V A R E F1 V SSA1
V A G N D 0 P 0.3
AN 1 P 0.1
V D D P P 0 .11 P 0.12
P 0.6
V SS
P 0.13
V DD
V DDP
P 3.3 P 3.0
D 2 9 V AGND1 D28 D27 D23 D20 D17 D16 D15 EC IN EC OUT D4 RD ADV BC1 1 D 30 D 26 D 22 D 21 D 18
V DD
V DD
RAM
V DDA1
D 31 D 24
T P .0 T P .2
T P .1 T P .3
V SS V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS V SS
T P .14 T P .15 T P .12 T P .13
P 2.12 P 2 .1 4 P 2 .1 3 P 2 .10 P 2.11 P 2 .8 P 2.9 P 2.5
D 25
V DDP
P 2.3
P 2.4 P 2.0
V DD
D 19 D 14 D 11 D9 D7 D5 D0 BC2 CODE 3
V SS V SS
T P .4 T P .6
V SS V SS
T P .5 T P .7
V SS V SS
V SS V SS
V SS
D 10 D8 D6 D2 D1 W A IT / IN D A0 A2 A4 5 A3 A6 A7 A9 6
V SS
P 1 .1 5 P 1 .1 2 P 1 .13
V DD
D 13 D 12
T P .10 T P .11 TP .8 TP .9
P 1.14 P 1 .1 1 P 2 .7 P 2 .2 P 1 .5 P 1 .1 0 P 1.4 P 1.8 P 1.1 P 2.6 P 1.9 TEST MODE 16
V DDP
P 1.3 BY PASS
P 1.7 P 1.6 P 1.0 HD RST
V DD
D3 RD/ WR BC0 BC3 2
V DD
SBRAM
A5 A 11 A 10
A8 A 15 A 14 A 12 8
A 19 A 16 A 18
CS3 CS2 A 23 A 22 10
OCD SE A21
TD O BRK OUT CS0 CS1 12
CPU C LK TCK
TR S T TDI A 13 A 17 14
P 1 .2 P 2 .1 BRK IN TMS 15
V SS
OSC
V DD
OSC
V DD
BAA A1 4
PO RST NMI N .C . 17
XTAL 2 XTAL 1 N .C . 18
V DD
C SE M U / CSOVL
V DD
A20 13
V DD
7
V DD
9
11
T he T race port is only available in the T C 1765T .
M C P 05009
Figure 3
TC1765 Pinning for P-LBGA-260 Package (top view)
Data Sheet
5
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol D[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 T3 R4 P4 R2 R1 R3 N4 P3 M4 N3 L4 M3 N2 M2 L3 M1 L1 K1 K2 K3 J1 J2 H2 H1 J4 H3 G2 G1 F1 E1 F2 H4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Definitions and Functions Pin In Functions Out EBU Data Bus Lines1)2) The EBU Data Bus Lines D[31:0] serve as external data bus. Data bus line 0 Data bus line 1 Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 Data bus line 8 Data bus line 9 Data bus line 10 Data bus line 11 Data bus line 12 Data bus line 13 Data bus line 14 Data bus line 15 Data bus line 16 Data bus line 17 Data bus line 18 Data bus line 19 Data bus line 20 Data bus line 21 Data bus line 22 Data bus line 23 Data bus line 24 Data bus line 25 Data bus line 26 Data bus line 27 Data bus line 28 Data bus line 29 Data bus line 30 Data bus line 31
Data Sheet
6
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol A[23:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CS0 CS1 CS2 CS3 CSEMU/ CSOVL T5 V4 U5 R6 V5 R7 T6 U6 R8 V6 U7 T7 V8 U14 U8 T8 T9 V14 U9 R9 V13 T11 V10 U10 U12 V12 T10 R10 V11 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Pin Definitions and Functions (cont'd) Pin In Functions Out EBU Address Bus Lines3)4) The EBU Address Bus Lines A[23:0] serve as address bus. Address bus line 0 Address bus line 1 Address bus line 2 Address bus line 3 Address bus line 4 Address bus line 5 Address bus line 6 Address bus line 7 Address bus line 8 Address bus line 9 Address bus line 10 Address bus line 11 Address bus line 12 Address bus line 13 Address bus line 14 Address bus line 15 Address bus line 16 Address bus line 17 Address bus line 18 Address bus line 19 Address bus line 20 Address bus line 21 Address bus line 22 Address bus line 23 Chip Select Lines3)5) Chip select output line 0 Chip select output line 1 Chip select output line 2 Chip select output line 3 Chip Select for Emulator Region / Chip Select for Emulator Overlay Memory3)5)
Data Sheet
7
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol Pin Definitions and Functions (cont'd) Pin In Functions Out EBU Control Lines1)5) The EBU control lines are required for controlling external memory or peripheral devices. Byte control line 0 Byte control line 1 Byte control line 2 Byte control line 3 Read control line Write control line Address valid output Wait input / End of burst input Burst address advance output Code fetch status output The CODE signal has the same timing as the chip select signals.
BC0 BC1 BC2 BC3 RD RD/WR ADV WAIT/IND BAA CODE
U2 V1 U3 V2 T1 T2 U1 R5 U4 V3
O O O O O O O I O O
Data Sheet
8
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol AN[23:0] Pin Definitions and Functions (cont'd) Pin In Functions Out ADC Analog Input Port The ADC Analog Input Port provides 24 analog input lines for the A/D converters ADC0 and ADC1. Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog input 20 Analog input 21 Analog input 22 Analog input 23
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23
A7 D6 B6 D5 A6 B5 C5 A5 A3 C4 C3 B3 D3 D4 E4 E3 A2 A1 B2 B1 C2 F4 F3 D2
I I I I I I I I I I I I I I I I I I I I I I I I
Data Sheet
9
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol P0 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 06) Port 0 is a 16-bit bi-directional general purpose I/O port that is also used as input/output for ASC0, SSC0, CAN, GPTU, ADC0, ADC1, and the DMA Controller. GPT0 GPTU I/O line 0 / AD0EXTIN0 ADC0 external trigger input 0 GPT1 GPTU I/O line 1 AD0EXTIN1 ADC0 external trigger input 1 DMREQ0A DMA request input 0A GPT2 GPTU I/O line 2 AD1EXTIN0 ADC1 external trigger input 0 DMREQ1A DMA request input 1A GPT3 GPTU I/O line 3 AD1EXTIN1 ADC1 external trigger input 1 GPT4 GPTU I/O line 4 / AD0EMUX0 ADC0 external multiplexer control 0 GPT5 GPTU I/O line 5 AD0EMUX1 ADC0 external multiplexer control 1 GPT6 GPTU I/O line 6 AD0EMUX2 ADC0 external multiplexer control 2 RXD0 ASC0 receiver input/output TXD0 ASC0 transmitter output SCLK0 SSC0 clock input/output MRST0 SSC0 master receive input / SSC0 slave transmit output MTSR0 SSC0 master transmit output / SSC0 slave receive input RXDCAN0 CAN receiver input 0 TXDCAN0 CAN transmitter output 0 RXDCAN1 CAN receiver input 1 TXDCAN1 CAN transmitter output 1
P0.0 P0.1
A10 D7
P0.2
B8
P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15
C7 A11 A12 D8 B9 A13 B10 A14 C9 C10 D10 A15 B11
I/O I I/O I I I/O I I I/O I I/O O I/O O I/O O I/O O I/O I/O I/O I O I O
Data Sheet
10
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol P1 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 16) Port 1 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN0 / OUT0 line of GPTA IN1 / OUT1 line of GPTA IN2 / OUT2 line of GPTA IN3 / OUT3 line of GPTA IN4 / OUT4 line of GPTA IN5 / OUT5 line of GPTA IN6 / OUT6 line of GPTA IN7 / OUT7 line of GPTA IN8 / OUT8 line of GPTA IN09 / OUT9 line of GPTA IN10 / OUT10 line of GPTA IN11 / OUT11 line of GPTA IN12 / OUT12 line of GPTA IN13 / OUT13 line of GPTA IN14 / OUT14 line of GPTA IN15 / OUT15 line of GPTA Port 26) Port 2 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN16 / OUT16 line of GPTA IN17 / OUT17 line of GPTA IN18 / OUT18 line of GPTA IN19 / OUT19 line of GPTA IN20 / OUT20 line of GPTA IN21 / OUT21 line of GPTA IN22 / OUT22 line of GPTA IN23 / OUT23 line of GPTA IN24 / OUT24 line of GPTA IN25 / OUT25 line of GPTA IN26 / OUT26 line of GPTA IN27 / OUT27 line of GPTA IN28 / OUT28 line of GPTA IN29 / OUT29 line of GPTA IN30 / OUT30 line of GPTA IN31 / OUT31 line of GPTA
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 P2
N18 R16 R15 M17 N16 P15 M18 L18 P16 U16 M16 L16 K17 K18 L15 K16
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
J18 T15 N15 J17 H18 J16 T16 M15 J15 H16 G18 H15 G15 G17 G16 F18
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
11
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol P3 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 36) Port 3 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN32 / OUT32 line of GPTA IN33 / OUT33 line of GPTA IN34 / OUT34 line of GPTA IN35 / OUT35 line of GPTA IN36 / OUT36 line of GPTA IN37 / OUT37 line of GPTA IN38 / OUT38 line of GPTA IN39 / OUT39 line of GPTA IN40 / OUT40 line of GPTA IN41 / OUT41 line of GPTA IN42 / OUT42 line of GPTA IN43 / OUT43 line of GPTA IN44 / OUT44 line of GPTA IN45 / OUT45 line of GPTA IN46 / OUT46 line of GPTA IN47 / OUT47 line of GPTA Port 46) Port 4 is an 8-bit bidirectional general purpose I/O port which also serves as input/output for the GPTA or external request input for the DMA controller. During hardware reset the port 4 lines are also used as start-up configuration selection inputs and PLL clock selection inputs. IN48 / OUT48 line of GPTA IN49 / OUT49 line of GPTA / DMREQ0B DMA request input 0B IN50 / OUT50 line of GPTA / DMREQ1B DMA request input 1B IN51 / OUT51 line of GPTA IN52 / OUT52 line of GPTA / CFG[0] IN53 / OUT53 line of GPTA / CFG[1] IN54 / OUT54 line of GPTA / CFG[2] IN55 / OUT55 line of GPTA / GPTA emergency shut down CFG[2:0]: Start-up Configuration Selection Inputs These pins are sampled during power-on reset (PORST = 0). The configuration inputs define the boot options of the TC1765 after a hardware reset operation.
12 V1.2, 2002-12
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 P4
F16 F15 E18 E16 E15 E17 D18 D17 C18 C17 B18 A18 C14 D15 B17 B16
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
D14 C13 A17 B15 C16 D13 C15 C12
I/O I/O I I/O I I/O I/O I/O I/O I/O
Data Sheet
TC1765
Preliminary Table 1 Symbol P5 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 56) Port 5 is a 5-bit bidirectional general purpose I/O port which also serves as input or output for ASC1 and SSC1. RXD1 ASC1 receiver input/output DMREQ0C DMA request input 0C TXD1 ASC1 transmitter output DMREQ1C DMA request input 1C SCLK1 SSC1 clock input/output MRST1 SSC1 master receive input / SSC1 slave transmit output MTSR1 SSC1 master transmit output / SSC1 slave receive input OCDS-2 Trace Port3) TP is the OCDS Level 2 Trace Port. The Trace port is only available in the TC1765T. The TP outputs are tristated during reset and deep sleep mode. Trace output 0 Trace output 1 Trace output 2 Trace output 3 Trace output 4 Trace output 5 Trace output 6 Trace output 7 Trace output 8 Trace output 9 Trace output 10 Trace output 11 Trace output 12 Trace output 13 Trace output 14 Trace output 15 JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. JTAG Module Clock Input JTAG Module Serial Data Input
P5.0 P5.1 P5.2 P5.3 P5.4 TP
D12 B13 B14 C11 A16
I/O I O I I/O I/O I/O O
TP.0 TP.1 TP.2 TP.3 TP.4 TP.5 TP.6 TP.7 TP.8 TP.9 TP.10 TP.11 TP.12 TP.13 TP.14 TP.15 TRST7)
G7 G8 H7 H8 L7 L8 M7 M8 M11 M12 L11 L12 H11 H12 G11 G12 R14
O O O O O O O O O O O O O O O O I
TCK7) TDI8)
T13 T14
I I
Data Sheet
13
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol TDO TMS8) OCDSE8) Pin Definitions and Functions (cont'd) Pin R12 V15 R11 In Functions Out O I I JTAG Module Serial Data Output3) JTAG Module State Machine Control Input OCDS Enable Input A low level on this pin during power-on reset (PORST = 0) enables the on-chip debug support (OCDS). In addition, the level of this pin during power-on reset determines the boot configuration. OCDS Break Input A low level on this pin causes a break in the chip's execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. OCDS Break Output3) A low level on this pin indicates that a programmable OCDS event has occurred. Non-Maskable Interrupt Input A high-to-low transition on this pin causes an NMI-Trap request to the CPU. Hardware Reset Input / Reset Indication Output6) Assertion of this open-drain bidirectional pin causes a synchronous reset of the chip through external circuitry. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, it is programmable whether this pin is activated or not. Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. During power-up of the TC1765, this pin must be held active (low). PLL Bypass Control Input This pin is sampled during power-on reset (PORST = 0). If BYPASS is at high level, direct drive mode operation of the clock circuitry is selected and the PLL is bypassed.
BRKIN8)
U15
I
BRKOUT
T12
O
NMI8)
U17
I
HDRST8)
P18
I/O
PORST
T17
I
BYPASS
N17
I
Data Sheet
14
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol XTAL1 XTAL2 Pin Definitions and Functions (cont'd) Pin U18 T18 In Functions Out I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. EBU Clock Output3) EBU Clock Input The ECIN pin is used to latch the data from external components into the EBU. This pin has to be connected to the ECOUT pin. Additional delay elements might be used to adapt to long delays at the address and data lines. CPU Clock Output3) General purpose clock output (can be disabled if not used). In addition, the OCDS-2 trace output data are synchronous to this clock. Test Mode Select Input For normal operation of the TC1765 this pin should be connected to VDD. Main Oscillator Power Supply (2.5 V)9) Main Oscillator Ground Core and EBU Power Supply (2.5 V)9)
ECOUT ECIN
P1 N1
O -
CPUCLK
R13
O
TEST MODE8)
V16
I
VDDOSC VSSOSC VDD
R18 R17 J3, P2, T4, V7, U11, U13, L2, F17, D11, V9
- - -
Data Sheet
15
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol Pin Definitions and Functions (cont'd) Pin L17, H17, D16, B12, C8 In Functions Out - Port 0 to 5 and Dedicated Pins Power Supply (3.3 - 5 V)10)
VDDP
VDDRAM G3 VDDSBRAM P17 VSS
D9, K4, K15, G9, G10, H9, H10, J7, J8, J9, J10, J11, J12, K7, K8, K9, K10, K11, K12, L9, L10, M9, M10
- - -
Power Supply for PMU Memories (2.5 V)9) Power Supply for DMU Memory (2.5 V)9) Used for normal and stand-by operating mode. Ground
Data Sheet
16
V1.2, 2002-12
TC1765
Preliminary Table 1 Symbol Pin Definitions and Functions (cont'd) Pin B4 A4 A9 B7 G4 D1 A8 C6 C1 E2 V17, V18 In Functions Out - - - - - - - - - - - ADC Analog Part Power Supply (5 V)10) ADC Analog Part Ground for VDDM ADC0 Analog Part Power Supply (2.5 V)9) ADC0 Analog Part Ground for VDDA0 ADC1 Analog Part Power Supply (2.5 V)9) ADC1 Analog Part Ground for VDDA1 ADC0 Reference Voltage10) ADC0 Reference Ground ADC1 Reference Voltage10) ADC1 Reference Ground10) Not Connected; reserved for future expansions
VDDM VSSM VDDA0 VSSA0 VDDA1 VSSA1 VAREF0 VAGND0 VAREF1 VAGND1
N.C.
1) 2) 3) 4) 5) 6) 7) 8) 9)
These pins have a drive capability of 600 A when used as outputs. These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUDPEN. These outputs have a drive capability of 600 A. These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUAPEN. These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUCPEN. These pins have a drive capability of 2.4 mA when used as outputs. These pins have an internal pull-down device connected. These pins have an internal pull-up device connected. The voltage on power supply pins marked with 10) has to be raised earlier or at least at the same time (= time window of 1 s) than on power supply pins marked with 9) (details see power supply section on Page 54). See note 9).
10)
Data Sheet
17
V1.2, 2002-12
TC1765
Preliminary Parallel Ports The TC1765 has 77 digital input/output port lines organized into four parallel 16-bit ports (Port 0 to Port 3), one 8-bit port (Port 4), and one 5-bit port (Port 5). Additionally, 24 analog input port lines are available. The External Bus Unit (EBU) is provided with dedicated data, address, and control lines. A 16-bit Trace Port is available only in the TC1765T. The digital parallel ports Port 0 to Port 5 can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. The on-chip External Bus Interface Unit allows to communicate with external memories, external peripherals, or external debugging devices. An overview on the port-to-peripheral unit assignment is shown in Figure 4. Note: For further details on the three pin classes of the TC1765 I/O pins see also Table 8 on Page 56):
E x tern al B u s Interfa ce D a ta B u s D [3 1 :0 ] A d dre ss B us A [2 3 :0 ] C o ntro l L in es TC 1765N TC1765T P a ralle l P o rts
G P IO P o rt 0 P o rt 1 P o rt 2 P o rt 3 P o rt 4
A ltern ate Fu n ctio ns G P TU / A S C 0 / S S C 0 / CAN / ADC0 / ADC1 G P TA G P TA G P TA G P TA / C FG ASC1 / SSC1
T P [1 5 :0 ] O C D S T rac e P o rt
(TC 1 7 6 5 T o n ly)
P o rt 5
A N [2 3 :0 ]
M C A 04981
Figure 4
Parallel Ports of the TC1765
Data Sheet
18
V1.2, 2002-12
TC1765
Preliminary Serial Interfaces The TC1765 includes five serial peripheral interface units: - Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1) - Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) - One TwinCAN Interface Asynchronous/Synchronous Serial Interfaces Figure 5 shows a global view of the functional blocks of the two Asynchronous/ Synchronous Serial interfaces ASC0 and ASC1.
C loc k C o ntro l
fASC0
A dd res s D eco d er E IR T B IR T IR R IR
RXD0 ASC0 M o du le (K ern e l) TXD0 P o rt 0 C on trol
P 0.7 / RXD0 P 0.8 / TXD0
Interru p t C o ntro l
To D M A
C loc k C o ntro l
fASC1
A dd res s D eco d er E IR T B IR T IR R IR
RXD1 ASC1 M o du le (K ern e l) TXD1 P o rt 5 C on trol
P 5.0 / RXD1 P 5.1 / TXD1
Interru p t C o ntro l
To D M A
M C B 05050
Figure 5
General Block Diagram of the ASC Interfaces
Data Sheet
19
V1.2, 2002-12
TC1765
Preliminary Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC module kernel. The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1765 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. Features: * Full-duplex asynchronous operating modes - 8-bit or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability * Half-duplex 8-bit synchronous operating mode - Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock) * Double buffered transmitter/receiver * Interrupt generation - On a transmitter buffer empty condition - On a transmit last bit of a frame condition - On a receiver buffer full condition - On an error condition (frame, parity, overrun error)
Data Sheet
20
V1.2, 2002-12
TC1765
Preliminary High-Speed Synchronous Serial Interfaces Figure 6 shows a global view of the functional blocks of the two High-Speed Synchronous Serial interfaces SSC0 and SSC1.
Slave Master
C loc k C o n tro l
f S SC 0
RXD TXD RXD TXD S lav e M a ste r P ort 0 C o ntrol P 0.1 1 / M TSR0 P 0.1 0 / M RST0 P 0.9 / SCLK0
A dd res s D ec od er E IR T IR R IR
SSC0 M o d ule (K e rne l)
Inte rrup t C o n tro l
To DM A
Slave Master
C loc k C o n tro l
fSSC 1
RXD TXD RXD TXD S lav e M a ste r P ort 5 C o ntrol P 5.4 / M TSR1 P 5.3 / M RST1 P 5.2 / SCLK1
A dd res s D ec od er E IR T IR R IR
SSC1 M o d ule (K e rne l)
Inte rrup t C o n tro l
To DM A
SCLK
SCLK
M C B 05051
Figure 6
General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 0 and Port 5. Each of the SSC modules is further supplied by separate clock control, interrupt control, address decoding, and port control logic. The SSC supports full-duplex and half-duplex serial synchronous communication up to 20 Mbit/s (@ 40 MHz module clock) with receive and transmit FIFO support. The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission
Data Sheet 21 V1.2, 2002-12
TC1765
Preliminary and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits: 2-bit to 16 bit - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock * Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock) * Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) * Three-pin interface - Flexible SSC pin configuration * 4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO) - Independent control of RXFIFO and TXFIFO - 2 to 16 bit FIFO data width - Programmable receive/transmit interrupt trigger level - Receive and transmit FIFO filling level indication - Overrun error generation - Underflow error generation
Data Sheet
22
V1.2, 2002-12
TC1765
Preliminary TwinCAN Interface Figure 7 shows a global view of the functional blocks of the TwinCAN module.
C lock C ontrol
fCAN
Tw inC A N M odule K ernel B itstream P rocessor
TXDC0 RXDC0 P ort C on trol TXDC1 E rror H a ndling C ontrol
A dd ress D ecode r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7
M essa ge B uffers
P 0.13 / TXD CAN0 P 0.12 / R XDC AN0
Interrupt C ontrol
Interrupt C ontrol
Tim ing C on trol
RXDC1
P 0.15 / TXD CAN1 P 0.14 / R XDC AN1
M C B 05 0 59
Figure 7
General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 0. The TwinCAN module is further supplied by a clock control, interrupt control, address decoding, and port control logic. The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames are handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as well as with extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module's resources to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Full-CAN functionality and the FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and convenient CAN bus traffic handling. Depending on the application, each of the thirty-two message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems, which decreases CPU load and improves the real time behavior of the entire system.
Data Sheet
23
V1.2, 2002-12
TC1765
Preliminary The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features: * * * * CAN functionality conforms to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 Mbit/s is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. * Full-CAN functionality: 32 message objects can be individually - Assigned to one of the two CAN nodes - Configured as transmit or receive object - Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm - Set up to handle frames with 11-bit or 29-bit identifiers - Provided with programmable acceptance mask register for filtering - Monitored via a frame counter - Configured to Remote Monitoring Mode * Up to eight individually programmable interrupt nodes can be used. * CAN Analyzer Mode for bus monitoring is implemented.
Data Sheet
24
V1.2, 2002-12
TC1765
Preliminary Timer Units The TC1765 includes two timer units: - General Purpose Timer Unit (GPTU) - General Purpose Timer Array (GPTA) General Purpose Timer Unit Figure 8 shows a global view of the General Purpose Timer Unit (GPTU) module.
C lo ck C o ntro l
fG PTU
A d dre ss D e co de r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 G P TU M o du le (K ern el)
IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 O UT0 O UT1 O UT2 O UT3 O UT4 O UT5 O UT6 O UT7 P ort C o ntro l
IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7
P 0.0 / G P T 0 P 0.1 / G P T 1 P 0.2 / G P T 2 P 0.3 / G P T 3 P 0.4 / G P T 4 P 0.5 / G P T 5 P 0.6 / G P T 6 N ot C on ne cted
M C B 05052
In terru pt C o ntro l
Figure 8
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs located at Port 0. The I/O has three timers (T0, T1, and T2) can operate independently from each other, or can be combined. General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU. Events generated in T0 or T1 can be used to trigger actions in T2. Timer overflow or underflow in T2 can be used to clock either T0 or T1. T0 and T1 can be concatenated to form one 64-bit timer.
Data Sheet
25
V1.2, 2002-12
TC1765
Preliminary Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow. * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers. * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events. * Two input pins can define a count option. Features of T2: * Count up or down is selectable * Operating modes: - Timer - Counter - Quadrature counter (incremental/phase encoded counter interface) * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins. * T2 events are freely assignable to the service request nodes.
Data Sheet
26
V1.2, 2002-12
TC1765
Preliminary General Purpose Timer Array Figure 9 shows a global block diagram of the General Purpose Timer Array (GPTA).
IO 0 IO 1 IO 14 IO 15 IO 16 IO 17 IO 30 IO 31 P o rt C o ntrol IO 32 IO 33 IO 46 IO 47 IO 48 IO 49 IO 54 IO 55
C loc k C o n tro l
fG PTA
G PTA M odule Kernel C loc k G e ne ration U n it F ilter & P res ca le r C e lls D u ty C y cle M e a su rem en t P h a se D is crim ina tor Lo gic D igital P h as e Lo ck ed Lo o p
IN 0 IN 1 IN 5 4 IN 5 5
P 1 .0 P 1 .1 P 1.1 4 P 1.1 5 P 2 .0 P 2 .1 P 2.1 4 P 2.1 5 P 3 .0 P 3 .1 P 3.1 4 P 3.1 5 P 4 .0 P 4 .1 P 4 .6 P 4 .7
M C B 05053
A dd res s D ec od er
IO Sharing Unit with Emergency Shut-Off
AS0 AS1 AS54 AS55
SR00 SR01 Inte rrup t C o n tro l S ig na l G e n era tio n U nit SR52 SR53 G T C 30 L TC 5 4 P T IN 0 0 P T IN 0 1 P T IN 1 0 P T IN 1 1 G lob al T im er C e lls G lo ba l Tim e rs Lo ca l T im e r C e lls
To DM A
O U T0 O U T1 O U T 54 O U T 55
A /D C o n ve rte r
Inte rrup t C o ntro l U nit
Figure 9
GPTA Module Block Diagram
The GPTA module has 56 input signals and 56 output signals which are connected with 56 Port 1, Port 2, Port 3, and Port 4 pins. The General Purpose Timer Array (GPTA) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. This architecture allows easy implementation and easy validation of any kind of timer functions.
Data Sheet
27
V1.2, 2002-12
TC1765
Preliminary The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: * Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. * Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. * Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities. * A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal's period. * Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated "Global Timer Cells". * Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an event that occurred at an external port pin or at an internal FPC output. A GTC may be also used to control an external port pin with the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. * Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs -- enabled in Timer Mode or Capture Mode -- can be clocked or triggered by - A prescaled GPTA module clock, - An FPC, PDL, DCM, PLL, or GTC output signal line, - An external port pin. Some input lines driven by processor I/O pads may be shared by a LTC and a GTC cell to trigger their programmed operation simultaneously. The following list summarizes all blocks supported: Clock Generation Unit: * Filter and Prescaler Cell (FPC): - Six independent units - Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce Filter) - fGPTA down-scaling capability - fGPTA/2 maximum input signal frequency in Filter Mode * Phase Discriminator Logic (PDL): - Two independent units - Two operating modes (2 and 3 sensor signals) - fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input signal frequency in 3-sensor mode * Duty Cycle Measurement (DCM): - Four independent units - 0 - 100% margin and time-out handling
Data Sheet
28
V1.2, 2002-12
TC1765
Preliminary - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Digital Phase Locked Loop (PLL): - One unit - Arbitrary multiplication factor between 1 and 65535 - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Signal Generation Unit: * Global Timers (GT): - Two independent units - Two operating modes (Free Running Timer and Reload Timer) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Global Timer Cell (GTC): - 32 independent units - Two operating modes (Capture, Compare and Capture after Compare) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Local Timer Cell (LTC): - 64 independent units - Three operating modes (Timer, Capture and Compare) - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Interrupt Control Unit: * 111 interrupt sources generating 54 service requests I/O Sharing Unit: * Interconnecting input and output lines from FPC, GTC, LTC and ports * Emergency function
Data Sheet
29
V1.2, 2002-12
TC1765
Preliminary Analog-to-Digital Converters The two on-chip ADC modules of the TC1765 are analog to digital converters with 8-bit, 10-bit or 12-bit resolution including sample & hold functionality. The A/D converters operate by the method of the successive approximation. A multiplexer selects between up to 16 analog input channels for each ADC module. The 24 analog inputs are switched to the analog input channels of the ADC modules by a fixed scheme. Conversion requests are generated either under software control or by hardware (GPTA). An automatic self-calibration adjusts the ADC modules to changing temperatures or process variations. Features: * * * * * * * * * * * * * * * * * * * 8-bit, 10-bit, 12-bit A/D Conversion Successive approximation conversion method Fast conversion times: e.g. 10-bit conversion (without sample time): 2.05 s Total Unadjusted Error (TUE) of 2 LSB @ 10-bit resolution Integrated sample and hold functionality 24 analog input pins / 16 analog input channels of each ADC module Fix assignment of 24 analog input pins to the 32 ADC0/ADC1 input channels Dedicated control and status registers for each analog channel Flexible conversion request mechanisms Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Flexible ADC module service request control unit Synchronization of the two on-chip A/D Converters Automatic control of an external analog input multiplexer for ADC0 Equidistant samples initiated by timer Two trigger inputs, connected with the General Purpose Timer Array (GPTA) Two external trigger input pins of each ADC for generating conversion requests Power reduction and clock control feature
Figure 10 shows a global view of the ADC module kernel with the module specific interface connections. The ADC modules communicate with the external world via five (ADC0) or two (ADC0) digital I/O lines and sixteen analog inputs. Clock control, address decoding, digital I/O port control, and service request generation is managed outside the ADC module kernel. The end of a conversion is indicated for each channel n (n = 0-15) by a pulse on the output signals SRCHn. These signals can be used to trigger a DMA transfer to read the conversion result automatically. Two trigger inputs and a synchronization bridge are used for internal control purposes.
Data Sheet
30
V1.2, 2002-12
TC1765
Preliminary
V S SA 1 V DDM1 V AG ND1 V DDA1 V SSM1 V AREF1 fADC
P ort 0 C ontrol P 0.0 / A D 0E X T IN 0 P 0.1 / A D 0E X T IN 1 P 0.4 / A D 0E M U X 0 P 0.5 / A D 0E M U X 1 P 0.6 / A D 0E M U X 2
C lo ck C o ntrol
A ddress D eco der AD C0 M od ule K ernel
Interrup t C o ntrol
S R [3 :0]
A IN 0 A IN 1 Analog Pad to ADC0/ADC1 Input Channel Connection
S R C H [1 5:0] To D M A P T IN 00 P T IN 01 G PTA P T IN 10 P T IN 11 S ynch ronizatio n B ridge A IN 0 A IN 1 A IN 1 4 A IN 1 5
AN0 AN1
A N 22 A N 23
A IN 1 3 A ddress D eco der A IN 1 5 AD C1 M od ule K ernel S R [3:0]
Interrup t C o ntrol
S R C H [15:0 ] To D M A
P ort 0 C ontrol
P 0.2 / A D 1E X T IN 0 P 0.3 / A D 1E X T IN 1
V AG N D 1 V D D A1 V SS M 1 V AR E F 1 V SS A 1 V DDM 1
M C B 0 50 5 4
Figure 10
General Block Diagram of the ADC Interface
Data Sheet
31
V1.2, 2002-12
TC1765
Preliminary On-Chip Memories The memory system of the TC1765 provides the following memories: * Program Memory Unit (PMU) with - 8 Kbytes Boot ROM (BROM) - 16 Kbytes Code Scratch-Pad RAM (SPRAM) - 1 Kbyte Instruction Cache (ICACHE) * Data Memory Unit (DMU) with - 32 Kbytes Data Memory (SRAM) - Can be used for standby operation during power-down states using a separate power supply
Data Sheet
32
V1.2, 2002-12
TC1765
Preliminary Address Map Table 2 defines the segment oriented address blocks of the TC1765 with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of segment 15 which includes the on-chip peripheral units. Table 2 TC1765 Block Address Map Size 2 GB Description Reserved DMU Acc. - via FPI DMU local via FPI PMU Acc.1) - PMU local cached non-cached via FPI via EBU or FPI via EBU or FPI via FPI via FPI
Seg- Address ment Range 0-7 8 9 10 0000 0000H 7FFF FFFFH 8000 0000H 8FFF FFFFH 9000 0000H 9FFF FFFFH A000 0000H AFFF FFFFH B000 0000H BDFF FFFFH BE00 0000H BEFF FFFFH BF00 0000H BFFF DFFFH BFFF E000H BFFF FFFFH 12 C000 0000H C000 3FFFH C000 4000H C7FF FEFFH C7FF FF00H C7FF FFFFH C800 0000H CFFF FFFFH
256 MB Reserved 256 MB Reserved 256 MB External Memory Space
11
224 MB External Memory Space mappable into Segment 10 16 MB -16 MB 8 KB External Emulator Space Reserved Boot ROM 4 Kbytes general purpose 4 Kbytes factory test support Local Code Scratch-Pad RAM (SPRAM) Reserved PMU Control Registers Reserved via FPI
PMU local
16 KB - 256 B -
PMU local
Data Sheet
33
V1.2, 2002-12
TC1765
Preliminary Table 2 TC1765 Block Address Map (cont'd) Size 32 KB - 256 B Description Local Data Memory (SRAM) Reserved DMU Registers via FPI non-cached non-cached DMU local DMU Acc. PMU Acc.1)
Seg- Address ment Range 13 D000 0000H D000 7FFFH D000 8000H D7FF FEFFH D7FF FF00H D7FF FFFFH D800 0000H DFFF FFFFH 14 E000 0000H EFFF FFFFH F000 0000H F000 3BFFH F000 3C00H F000 3DFFH F000 3E00H F00F FFFFH F010 0000H F010 0BFFH F010 0C00H FFFE FEFFH FFFE FF00H FFFE FFFFH FFFF 0000H FFFF FFFFH
1)
256 MB Reserved 256 MB External Peripheral and Data Memory Space -16 KB 512 B - 12 x 256 B - 256 B 64 KB On-Chip Peripherals & Ports DMA Registers Reserved CAN Module Reserved CPU Slave Interface Registers (CPS) Core SFRs + GPRs via FPI not possible via FPI not possible
15
The PMU can access external memory directly ("via EBU", only instruction accesses) or via the FPI Bus ("via FPI"). If both paths are possible as defined in this column, selection is done via SCU_CON.EXTIF.
Data Sheet
34
V1.2, 2002-12
TC1765
Preliminary Table 3 SCU - BCU STM OCDS EBU - GPTU ASC0 ASC1 SSC0 SSC1 - GPTA - ADC0 ADC1 - P0 P1 P2 P3 P4 P5 - DMA - CAN1) Block Address Map of Segment 15 Address Range F000 0000H - F000 00FFH F000 0100H - F000 01FFH F000 0200H - F000 02FFH F000 0300H - F000 03FFH F000 0400H - F000 04FFH F000 0500H - F000 05FFH F000 0600H - F000 06FFH F000 0700H - F000 07FFH Size 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 8 x 256 Bytes - 2 x 256 Bytes 2 x 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 2 x 256 Bytes - 12 x 256 Bytes System Control Unit Reserved Bus Control Unit System Timer On-Chip Debug Support External Bus Unit Reserved General Purpose Timer Unit
Symbol Description
Async./Sync. Serial Interface 0 F000 0800H - F000 08FFH Async./Sync. Serial Interface 1 F000 0900H - F000 09FFH High-Speed Synchronous Serial Interface 0 High-Speed Synchronous Serial Interface 1 Reserved General Purpose Timer Array Reserved Analog-to-Digital Converter 0 Analog-to-Digital Converter 1 Reserved Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Reserved DMA Controller Reserved Controller Area Network Module F000 0A00H - F000-0AFFH F000 0B00H - F000-0BFFH F000 0C00H - F000 17FFH F000 1800H - F000 1FFFH F000 2000H - F000 21FFH F000 2200H - F000 23FFH F000 2400H - F000 25FFH F000 2600H - F000 27FFH F000 2800H - F000 28FFH F000 2900H - F000 29FFH F000 2A00H - F000 2AFFH F000 2B00H - F000 2BFFH F000 2C00H - F000 2CFFH F000 2D00H - F000 2DFFH F000 2E00H - F000 3BFFH F000 3C00H - F000 3DFFH F000 3E00H - F00F FFFFH F010 0000H - F010 0BFFH
Data Sheet
35
V1.2, 2002-12
TC1765
Preliminary Table 3 - CPU Block Address Map of Segment 15 (cont'd) Address Range Size Reserved Slave Interface Registers (CPS) Reserved Memory Protection Registers Reserved Core Special Function Registers (CSFRs) General Purpose Registers (GPRs)
1)
Symbol Description
F010 0C00H - FFFE FEFFH - FFFE FF00H - FFFE FFFFH 256 Bytes FFFF 0000H - FFFF BFFFH - FFFF C000H - FFFF EFFFH 12 Kbytes FFFF F000H - FFFF FCFFH - FFFF FE00H - FFFF FEFFH 256 Bytes FFFF FF00H - FFFF FFFFH 256 Bytes
Core Debug Registers (OCDS) FFFF FD00H - FFFF FDFFH 256 Bytes
Access to unused address regions within this peripheral unit don't generate a bus error.
Data Sheet
36
V1.2, 2002-12
TC1765
Preliminary Memory Protection System The TC1765 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1765, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. Because the TC1765 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range.
Data Sheet
37
V1.2, 2002-12
TC1765
Preliminary On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1765, such as the CPU and onchip peripheral components. The FPI Bus also interconnects the TC1765 to external components by way of the External Bus Controller Unit (EBU). The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications. The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 160 Mbyte/s can be achieved with a 40 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Features: * * * * * * Supports multiple bus masters Supports demultiplexed address/data operation Address and data buses are 32 bits wide Data transfer types include 8-, 16-, and 32-bit sizes Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption
Data Sheet
38
V1.2, 2002-12
TC1765
Preliminary External Bus Unit The External Bus Unit (EBU) of the TC1765 is the interface between external memories and peripheral units and the internal memories and peripheral units. The basic structure of the EBU is shown in Figure 11.
PM U w ith o n -ch ip P ro ga m M em o ry
B u rst M o de Instru ction F etch e s B IFU
10
C on trol L in e s C hip S elec t L in e s A [2 3 :0 ]
5
TriC ore CPU
F P I B us
EBU
DM U w ith o n -ch ip D ata M em ory T o P e rip he ral U n its a nd D M A
FB U
D [31 :0] E C IN ECO UT
M C A 04983
Figure 11
EBU Structure and Interfaces
The EBU consists of two parts and is used for the following two operations: * FBU (FPI Bus Unit): - Communication with external memories or peripheral units via the FPI Bus - Non-burst instruction fetches * BIFU (Burst Instruction Fetch Unit): - Instruction fetches from the PMU to external Burst Flash program memories with 16-bit and 32-bit data width The EBU controls all transactions required for these two operations and in particular handles the arbitration between these two tasks. The types of external devices/Bus modes controlled by the FBU are: - - - - - - - INTEL style peripherals (separate RD and WR signals) MOTOROLA style peripherals (OE and R/W) ROMs, EPROMs Static RAMs Peripherals with demultiplexed A/D bus Burst Mode Flash Memories 8-, 16- and 32-bit data bus width
Data Sheet
39
V1.2, 2002-12
TC1765
Preliminary DMA Controller The Direct Memory Access (DMA) Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each of the two blocks in the DMA controller, block 0 and block 1 (see Figure 12), provides four DMA channels with sixteen DMA request inputs. The request assignment unit in each sub-block assigns one DMA request input to each DMA channel. The control unit includes a third request unit dedicated especially for request control through I/O pins. This unit connects two of eight request inputs with two request outputs which can be then wired externally of the DMA controller module to the request inputs of the two DMA controller blocks. Request assignment unit 2 evaluates pulses or levels by its edge detect and level select logic. Features: * 8 independent DMA channels (4 per DMA block) - 4 DMA selectable request inputs per DMA channel - Fixed priority of DMA channels within a DMA block - Software and hardware DMA request generation * Support of FPI Bus to FPI Bus DMA transactions * Individually programmable operation modes for each DMA channel - Single mode: stops and disables DMA channel after a predefined number of DMA transfers - Continuous mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated * Full 32-bit addressing capability of each DMA channel - 4 Gbyte address range - Source and destination transfer individually programmable in steps from 0 to 255 bytes - Support of circular buffer addressing mode * Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit * Register set for each DMA channel - Source and destination start address register - Source and destination end address register - Channel control and status register - Offset and transfer count register * Bus bandwidth allocation * Flexible interrupt generation Figure 12 shows the TC1765 specific implementation details and interconnections of the DMA module. The DMA module is further supplied by a separate clock control, address decoding, interrupt control, port control logic.
Data Sheet
40
V1.2, 2002-12
TC1765
Preliminary
P 0.1 / DM REQ 0A P 4.1 / DM REQ 0B P 5.0 / DM REQ 0C DM A Controller S u b-B lo ck 0 DMA C h an ne ls 0 0-0 3 R e qu es t A ss ig n. U nit 0 16 ASC0 ASC1 SSC0 4 A d dre ss D e co de r SR0 SR1 In terru pt C o ntro l SR6 SR7 S u b-B lo ck 1 DMA C h an ne ls 1 0-1 3 R e qu es t A ss ig n. U nit 1 16 ADC1 C on trol U n it R e q ue st A s sign . U n it 2 REQO0 REQO1 4 DMA R e q ue st W irin g M atrix SSC1 G P TA 3
(G T C 3 0 )
C lo ck C o ntro l
fDMA
ADC0
G P TA 3
(L T C 5 4 )
P 0.2 / DM REQ 1A P 4.2 / DM REQ 1B P 5.1 / DM REQ 1C
M C B 04965
Figure 12
DMA Module Block Diagram with Interconnections
Data Sheet
41
V1.2, 2002-12
TC1765
Preliminary System Timer The TC1765's System Timer (STM) is designed for global system timing applications requiring both high precision and long range. The STM has the following features: * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock fSTM (identical to the system clock fSYS) Counting starts automatically after a reset operation (except a hardware reset)
The STM is an upward counter, running with the system clock frequency (fSTM = fSYS). It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256 x 1 / fSTM. At fSTM = 40 MHz, for example, the STM counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing.
STM M odule
f ST M
PORST
55
47
39
31
23
15
7
56 -B it S y ste m Tim e r
C lo ck C o ntro l
E na b le / D isa ble
00 H 00 H T IM 5
CAP T IM 6
A dd res s D eco d er
TIM 4 T IM 3 T IM 2 T IM 1 TIM 0
M C A 04795
Figure 13
Data Sheet
Block Diagram of the System Timer Module
42 V1.2, 2002-12
TC1765
Preliminary Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1765 in a user-specified time period. When enabled, the WDT will cause the TC1765 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1765 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard "Watchdog" function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). A further enhancement in the TC1765's Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features: * 16-bit Watchdog counter * Selectable input frequency: fSYS/256 or fSYS/16384 * 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes * Incorporation of the ENDINIT bit and monitoring of its modifications * Sophisticated password access mechanism with fixed and user-definable password fields * Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. * Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. * Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. * Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. * Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1765 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Data Sheet
43
V1.2, 2002-12
TC1765
Preliminary * Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. System Control Unit The System Control Unit (SCU) of the TC1765 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: * Reset Control - Generation of all internal reset signals - Generation of external HDRST reset signal * PLL Control - PLL_CLC Clock Control Register * Power Management Control - Enabling of several power-down modes - Control of the PLL in power-down modes * Watchdog Timer * Trace Control and Trace Status indication * Pull-up/pull-down I/O control * Device Identification
Data Sheet
44
V1.2, 2002-12
TC1765
Preliminary Interrupt System An interrupt request is serviced by the CPU. Interrupt requests are also called "Service Requests" because they are serviced by a "Service Provider", the CPU. Each peripheral unit in the TC1765 typically generates service requests. Additionally, the Bus Control Unit, the Debug Unit, the DMA controller, and even the CPU itself can generate service requests. Several peripheral units are able to generate in parallel to a service request DMA requests to the DMA Controller. As shown in Figure 14, each TC1765 unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where "mod" is the identifier of the service requesting unit and "x" an optional index. The Interrupt arbitration bus connects the SRNs with the Interrupt Control Unit, which handles interrupt arbitration among competing interrupt service requests. Units which can generate service requests are: - - - - - - - - - - - General Purpose Timer Unit (GPTU) with 8 SRNs General Purpose Timer Array (GPTA) with 54 SRNs Two High-Speed Synchronous Serial Interfaces (SSC0/SSC1) with 3 SRNs each Two Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) with 4 SRNs each TwinCAN controller with 8 SRNs Two Analog/Digital Converters (ADC0/ADC1) with 4 SRNs each Bus Control Unit (BCU) with 1 SRN DMA Controller Processor (DMA) with 8 SRNs Central Processing Unit (CPU) with 4 SRNs Debug Unit (OCDS) with 1 SRN Central Processing Unit (CPU) with 4 SRNs (software activated)
External interrupt inputs in TC1765 are available using the input pins connected to the General Purpose Timer Unit (GPTU). Each of the seven GPTU I/O pins can be used as an external interrupt input, using the Service Request Nodes of the GPTU module. Additionally, such an external interrupt input can also trigger a timer function.
Data Sheet
45
V1.2, 2002-12
TC1765
Preliminary
DMA R e qu es t B us
S e rvice R eq u esto rs G P TU 1 2 2 2 2 G PTA SSC0 SSC1 ASC0 ASC1 CAN DM A 6 6 ADC0 ADC1 BCU D eb ug U nit 8 54 3 3 4 4 8 8 4 4 1 1
S e rvice R e qu es t N o de s 8 SRNs 54 SRNs 3 SRNs 3 SRNs 4 SRNs 4 SRNs 8 SRNs 8 SRNs 4 SRNs 4 SRNs 1 SRN 1 SRN 8 54 3
Inte rrup t A rb itra tio n B us
4 3 4 4
4 SRNs In terru pt C o ntro l U nit ICU
4
S oftw are Inte rru p ts
C PU Int. A ck . CCPN
8 8 4 4 1 1
Int. R e q . P IP N
M C B 04993
Figure 14
Block Diagram of the TC1765 Interrupt System
Data Sheet
46
V1.2, 2002-12
TC1765
Preliminary Boot Options The TC1765 booting schemes provides a number of different boot options for the start of code execution. Table 4 shows the boot options available in the TC1765. Table 4 OCDSE 1 TC1765 Boot Selections BRKIN 1 CFG[2:0] Type of Boot 000B 001B 010B 011B 100B Start from Boot ROM Entry Point 1 Start from Boot ROM Entry Point 2 Start from Boot ROM Entry Point 3 Start from Boot ROM Entry Point 4 External memory as master directly PMU - EBU External memory via PMU - FPI Bus - EBU Reserved; don't use these combinations. Go to halt with EBU enabled as master Go to halt with EBU disabled Go to external emulator - space Tri-state chip (deep sleep) - BE00 0000H - - - External Memory A000 0000H Boot Source PC Start Value Boot ROM BFFF FFFCH
101B 110B 111B 0 1 100B or 101B all other combinations 0 1 0 0 - -
Data Sheet
47
V1.2, 2002-12
TC1765
Preliminary Power Management System The TC1765 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: * * * * Run Mode Idle Mode Sleep Mode Deep Sleep Mode
Table 5 describes the features of the power management modes. Table 5 Mode Run Idle Power Management Mode Summary Description The system is fully operational. All clocks and peripherals are enabled, as determined by software. The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. The system clock continues to be distributed only to those peripherals programmed to operate in Sleep Mode. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM).
Sleep
Deep Sleep
Data Sheet
48
V1.2, 2002-12
TC1765
Preliminary On-Chip Debug Support The On-Chip Debug Support (OCDS) of the TC1765 consists of four building blocks: * OCDS module in the TriCore CPU - On-chip breakpoint hardware - Support of an external break signal * Trace module - Outputs 16 bits each fSYS system clock cycle at TP[15:0] with pipeline status information, PC bus information, and breakpoint qualification information * DMA Controller Trace - Indication of address counter updates * Debugger Interface Cerberus - Provided for debug purposes of emulation tool vendors - Accessible through a JTAG standard interface with dedicated JTAG port pins Figure 15 shows a basic block diagram of the building blocks.
.
FPI Bus
16 DM A C ontroller Trace SCU T ra ce C o n tro l & S tatu s 16 T P [15 :0] (T C 1 76 5 T o nly) BRKOUT
OCDS/TCU
TriCore CPU
16 B R K IN O CDSE
TDI TDO Cerberus & JTA G TM S TCK TRST
M C B 04995
JT A G I/O L in es
Figure 15
OCDS Basic Block Diagram
Data Sheet
49
V1.2, 2002-12
TC1765
Preliminary Clock Generation Unit The Clock Generation Unit (CGU) in the TC1765, shown in Figure 16, consists of an oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it looses its lock on the external clock. In general, the CGU is controlled through the System Control Unit (SCU) module of the TC1765.
C lock G eneration U nit CGU XTAL1 O scilla tor f O S C C ircu it X TA L2 N D ivid er P LL
&
P h a se D etec t.
VCO
fVCO
K D ivid e r
1 MUX 0
S yste m _ C LK
fSYS
L o ck D ete ctor
O SC_O K BYPASS System Control Unit SCU
D e ep S lee p
LO CK
K D IV
PLLBYP
R e giste r P LL _ C L C
M C A 04974
Figure 16
Clock Generation Unit Block Diagram
Data Sheet
50
V1.2, 2002-12
TC1765
Preliminary PLL Operation The fVCO clock of the PLL has a frequency which is a multiple of the externally applied clock fOSC. The factor for this is controlled through the fix divider value N (N = 10) applied to the divider in the feedback path. The K-Divider is defined by bit field KDIV. Table 6 lists the possible values for KDIV and the resulting division factor. The VCO output frequency and the resulting system clock is determined by:
fVCO = 10 x fOSC
fSYS = fVCO / K =
10 x fOSC K
Table 6 Selected Factor 2 4 52) 6 8 92) 10 16
1) 2)
Output Frequencies fSYS Derived from Various Output Factors K-Factor KDIV 000B 010B 011B 100B 101B 110B 111B 001B
fSYS fVCO =
150 MHz 751) 37.5 30 24.5 18.75 16.67 15 9.38
fVCO =
160 MHz 801) 40 32 26.67 20 17.78 16 10
fVCO =
200 MHz 1001) 501) 40 33.33 25 22.22 20 12.5
Duty Cycle [%] 50 50 40 50 50 44 50 50
These combinations cannot be used because the maximum system clock of 40 MHz is exceeded. These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).
Data Sheet
51
V1.2, 2002-12
TC1765
Preliminary Recommended Oscillator Circuits The oscillator circuit, designed to work with both, an external crystal oscillator or an external stable clock source, basically consists of an inverting amplifier with XTAL1 as input and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be used, connected to both pins, XTAL1 and XTAL2. The on-chip oscillator frequency can be within the range of 4 MHz to 16 MHz. When using an external clock signal it must be connected to XTAL1. XTAL2 is left open (unconnected). For direct drive operation without PLL, the frequency of an external clock must not exceed 40 MHz. Figure 17 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode.
V DDO SC
V DDO SC
X T A L1 4 -16 MHz TC 1765 Oscillator X T A L2
E xte rna l C loc k S ign al
XTAL1 TC1765 O scillator XTAL2
C1
C2 V SS O S C V SSOSC
M C B 04996
Figure 17
Oscillator Circuitries
For the oscillator of the TC1765 the following external passive components are recommended: - Crystal: max. 16 MHz - C1, C2: 10 pF A block capacitor between VDDOSC and VSSOSC is recommended, too. - C1, C2: 12 pF Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.
Data Sheet
52
V1.2, 2002-12
TC1765
Preliminary Power Supply Figure 18 shows the TC1765's power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. Also the operation margin is improved in sensitive modules like the A/D converter by noise reduction.
VDDA0
(2.5 V)
VDDM
(5 V)
VDDA1
(2.5 V)
VSSA0
VSSM
VSSA1
TC1765
ADC0
ADC1
Control Logic
Control Logic
DMU
PMU
GPIO Ports (P0-P5) & dedicated Pins
CPU & Control & Peripherals EBU, TP
OSC
VDDSBRAM
(2.5 V)
VDDRAM
(2.5 V)
VDDP
(3.3 - 5 V)
VDD
(2.5 V)
VDDOSC
(2.5 V)
VSS
VSS
VSS
VSS
VSSOSC
MCD05227
Figure 18
TC1765 Power Supply Concept
Data Sheet
53
V1.2, 2002-12
TC1765
Preliminary Ports Power Supply The TC1765's port power supply concept is shown in Figure 19. The External Bus Unit (EBU) I/O lines are in the core and EBU VDD power supply group for 2.5 V nominal operating voltage. The general purpose input/outputs (GPIOs) provide 3.3 to 5 V nominal voltage input/output acceptance and drive characteristics.
VDD
(2.5 V)
VDDP
(3.3 - 5 V)
VSS
EBU I/O Lines (Pads) & Schmitt Trigger
Ports 0 to 5 (Pads) & Schmitt Trigger
Port Logic
MCA05226
Figure 19
Ports Power Supply Concept
Power-up Sequence During Power-up the reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the difference between VDDP and VDD never drops below -0.5 V. Power Loss If VDDP is dropping below VDD, external circuitry in the power supply has to ensure, that VDD is also limited to the same level. If VDDI is dropping below the operating range, VDDP may stay active. Powering Down During powering down (falling of the supply voltages from their regular operating values to zero), it has to be ensured, that the difference between VDDP and VDD never drops below -0.5 V.
Data Sheet
54
V1.2, 2002-12
TC1765
Preliminary Identification Register Values Table 7 Short Name PMU_ID DMU_ID SCU_ID MANID CHIPID RTID BCU_ID STM_ID JPD_ID EBU_ID GPTU_ID ASC0_ID ASC1_ID SSC0_ID SSC1_ID GPTA_ID ADC0_ID DMA_ID CAN_ID CPU_ID TC1765 Identification Registers Address C7FF FF08H D7FF FF08H F000 0008H F000 0070H F000 0074H F000 0078H F000 0208H F000 0308H F000 0408H F000 0508H F000 0708H F000 0808H F000 0908H F000 0A08H F000 0B08H F000 1808H F000 2208H F000 3F08H F010 0008H FFFE FF08H Value 0006 C003H 0007 C003H 0003 C003H 0000 1820H 0000 8601H 0000 0000H 0000 6A05H 0000 C002H 0000 6301H 0005 C004H 0001 C002H 0000 4401H 0000 4401H 0000 4525H 0000 4525H 0002 C002H 0000 3103H 0018 C001H 0000 4110H 0000 0202H
Data Sheet
55
V1.2, 2002-12
TC1765
Preliminary Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1765 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the TC1765 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the TC1765. Pin Classes The TC1765 has three classes of digital I/O pins: - Class A pins, which are 3.0 to 5.25 V voltage pins - Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V) - Class C pins, which are 2.5 V nominal voltage pins only Table 8 shows the assignments of all digital I/O pins to pin classes and to VDD power supply pins. Table 8 Pins Port 0 to Port 5, BYPASS, HDRST D[31:0], A[23:0], CS[3:0], CSEMU/CSOVL, BC[3:0], RD, RD/WR, ADV, WAIT/IND, BAA, CODE, TRST, TCK, TDI, TDO, TMS, ODCSE, BRKIN, BRKOUT, NMI, PORST, ECOUT, ECIN, CPUCLK, TESTMODE, TP[15:0] XTAL1, XTAL2 No pins assigned Assignments of Digital Pins to Pin Classes and Power Supply Pins Pin Classes Class A (3.0 to 5.25 V) Class B (nominal 2.5 V) Power Supply
VDDP VDD
VSS
Class C (nominal 2.5 V) (nominal 2.5 V)
VDDOSC VDDRAM VDDSBRAM
VSSOSC VSS
Data Sheet
56
V1.2, 2002-12
TC1765
Preliminary Absolute Maximum Ratings Parameter Ambient temperature Symbol -40 -65 - -0.5 -0.5 Limit Values min. max. 125 150 150 6.2 3.25 Unit Notes
TA TA Storage temperature Junction temperature TJ Voltage on VDDP with respect to VDD VSS VDD Voltage on VDD, VDDOSC, VDDRAM and VDDSBRAM with respect to VSS Voltage on any Class A input pin VIN with respect to VSS Voltage on any Class B input pin VIN with respect to VSS Voltage on any Class C input pin VIN with respect to VSS IIN Input current on any pin during
overload condition Absolute sum of all input currents IIN during overload condition
C C C
V V
under bias - under bias see Table 8 -
-0.5 -0.5 -0.5 -10 -
VDD + 0.5 V
3.7 V V mA mA
- - - - -
VDDOSC
+ 0.5 10 |100|
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
57
V1.2, 2002-12
TC1765
Preliminary Package Parameters (P-LBGA-260) Parameter Power dissipation Thermal resistance Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1765. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Digital supply voltage
1)
Symbol
Limit Values min. max. 0.9 24.8 - -
Unit Notes W -
PDISS RTHA
K/W Chip to ambient
Symbol
Limit Values min. max. 5.252) 2.75
3)
Unit Notes V V Class A pins Class B and Class C pins4)
4)5)
Digital ground voltage Ambient temperature under bias Analog supply voltages Analog reference voltage Analog ground voltage Analog input voltage CPU clock Overload current Short circuit current Absolute sum of overload + short circuit currents External load capacitance
Data Sheet
VDDP VDD VDDOSC VDDRAM VDDSBRAM VSS TA VDDA VDDM VAREF VAGND VAIN fSYS IOV ISC
|IOV| + |ISC|
3.0 2.3
2.25 0 -40 2.25 4.5 4
2.75 +125 2.75 5.25
V V
- - - -
6)
C
V V V V V mA mA mA pF
VDDM +
0.05
VSSA 0.05
VSSA +
0.05
7)
VAGND
- -10 -10 - -
58
VAREF
40 10 10 |50| 50
-
8)9)10) 5)6)11) 9)
MHz -
CL
-
V1.2, 2002-12
TC1765
Preliminary
1)
Digital supply voltages applied to the TC1765 must be static regulated voltages which allow a typical voltage swing of 10%. Voltage overshoot to 6.5 V is permissible, provided that the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 hour. Voltage overshoot to 4 V is permissible, provided that the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 hour. In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at the same voltage level during normal operating mode. This condition is typically achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply VDDSBRAM is used. The minimum voltage at pin VDDSBRAM during TC1765 power down mode is 1.8 V in order to keep the contents of SBRAM valid. The core power supply VDD must be below the standby power supply VDD < VDDSBRAM + 0.3 V. The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Not 100% tested, guaranteed by design and characterization. Applicable for analog inputs. Applicable for digital inputs.
2)
3)
4)
5)
6)
7)
8)
9) 10) 11)
Data Sheet
59
V1.2, 2002-12
TC1765
Preliminary DC Characteristics Input/Output DC-Characteristics
VSS = 0 V; TA = -40 C to +125 C;
Parameter1) Symbol Limit Values min. Class A Pins (VDDP = 3.0 to 5.25 V) Output low voltage2) max. Unit Test Conditions
VOL CC -
0.45
V
0.2 x
V
VDDP
Output high voltage2) VOH CC 0.7 x - V
VDDP
V
Input low voltage5)
VIL
SR
-0.5
0.8 0.45 x
V V V V V
IOL = 2.4 mA3) IOL = 600 A4) VDDP = 4.5 to 5.25 V IOL = 2.4 mA IOL = 600 A4) VDDP = 3.0 to 4.49 V IOH = -2.4 mA IOH = -600 A4) VDDP = 4.5 to 5.25 V IOH = -2.4 mA IOH = -600 A4) VDDP = 3.0 to 4.49 V VDDP = 4.5 to 5.25 V
(TTL)
VDDP
0.2 x Input high voltage5)
VDDP = 4.5 to 5.25 V (CMOS) VDDP = 3.0 to 4.49 V (CMOS) VDDP = 4.5 to 5.25 V
(TTL)
VIH
SR
2.0 0.73 x
VDDP VDDP
+ 0.5
VDDP = 3.0 to 5.25 V
(CMOS)
VDDP
Pull-up current6)7) |IPUH| CC - |IPUL| CC 120 Pull-down current8)7) |IPDL| CC - |IPDH| CC 120 10 600 10 700
A A A A
VOUT = VDDP - 0.02 V VOUT = 0.5 x VDDP VOUT = 0.02 V VOUT = 0.5 x VDDP
Data Sheet
60
V1.2, 2002-12
TC1765
Preliminary Input/Output DC-Characteristics (cont'd)
VSS = 0 V; TA = -40 C to +125 C;
Parameter1) Symbol Limit Values min. Class B Pins (VDDP05 = 2.30 to 2.75 V) Output low voltage max. Unit Test Conditions
VOL CC -
0.2 x
V V V V V V
IOL = 2.4 mA IOL = 600 A IOH = -2.4 mA IOH = -600 A
- -
VDD
0.45 Output high voltage Input high voltage Input low voltage Pull-up current
6)7)
VOH CC 0.7 x VDD 0.9 x VDD VIH SR 0.7 x VDD VIL SR -0.5
|IPUH| CC - |IPUL| CC 50
- - 3.7 0.2 x
VDD
10 250 10 300
A A A A
Pull-down current8)7) |IPDL| CC - |IPDH| CC 40 Class A and B Pins Input Hysteresis HYS CC 0.030 x
VOUT = VDD - 0.02 V VOUT = 0.5 x VDD VOUT = 0.02 V VOUT = 0.5 x VDD
-
V nA mA
VDDx9)
CMOS only10) VDDx limits see11) 0 V < VIN < VDDx9)
14)10)
Input leakage current IOZ2 CC - (Digital I/O) Peak short-circuit current Peak back-drive current (per digital pin) Peak time & period time12)13)
500 20
ISCBDpeak -
SR
Constant short-circuit ISCBDcons - SR current Constant back-drive current (per digital pin)
Data Sheet 61
10
mA
14)10)
V1.2, 2002-12
TC1765
Preliminary Input/Output DC-Characteristics (cont'd)
VSS = 0 V; TA = -40 C to +125 C;
Parameter1) Pin capacitance10) (Digital I/O) Symbol Limit Values min. max. 10 pF Unit Test Conditions
CIO
CC -
f = 1 MHz TA = 25 C
Class C Pins (VDDOSC = 2.30 to 2.75 V), see Page 68
1)
All Class A pins of the TC1765 are equipped with Low-Noise output drivers, which significantly improve the device's EMI performance. These Low-Noise drivers deliver their maximum current only until the respective target output level is reached. After that the output current is reduced. This results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified in column "Test Conditions", is delivered in any case. This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain mode the output will float and the voltage results from the external circuitry. Output drivers in high current mode. Condition for output driver in dynamic current mode & low current mode - guaranteed by design characterization. Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated pins which have CMOS input characteristics. The maximum current can be drawn while the respective signal line remains inactive. The two pull-up/pull-down current test conditions for VOUT cover the curves as shown in Figure 20 and Figure 21. All pull-up/pull-down currents are given as absolute values. The minimum current must be drawn in order to drive the respective signal line active. In case of Class B pins VDDx = VDD. In case of Class A pins VDDx = VDDP. Guaranteed by design characterization. The test condition for Class A pins is: VDDP = 4.5 to 5.25 V; for Class B pins: VDD = 2.3 to 2.75 V; The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral of ISCBDpeak over the peak period is thus limited to 10 mA (provided: ISCBDpeak 20 mA). To be defined for Class B pads. Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. VSCBD > VDDP + 0.5 V or VSCBD < VSS - 0.5 V) or a short circuit condition occurs on the respective pin. The absolute sum of input ISCBD and IOV currents on all port pins must not exceed 100 mA at any time. The supply voltage (VDDP and VSS) must remain within the specified limits. Under shortcircuit conditions the corresponding pin is not ready for use. In case of Class B pins VDDx = VDD. In case of Class A pins VDDx = VDDP.
2)
3) 4)
5)
6) 7)
8) 9) 10) 11) 12)
13) 14)
Data Sheet
62
V1.2, 2002-12
TC1765
Preliminary Pull-Up/Pull-Down Characteristics
Pull-up 700 A 700 A
Pull-down Best Case
I
600 Best Case 500 400 Nominal 300 200 100 0 0
I
600 500 400 300 200 100 0 0
Nominal
Worst Case
Worst Case
1
2
3
4
5V6
1
2
3
4
5V6
V
V
MCD05139
Figure 20
Pull-Up/Pull-Down Characteristics of Class A Pins
Data Sheet
63
V1.2, 2002-12
TC1765
Preliminary
Pull-up 250 A 250 A Best Case 200
Pull-down
I
I
200 Best Case
150 Nominal
150 Nominal
100 Worst Case 50
100
50
Worst Case
0 0
0.5
1
1.5
2
2.5 V 3
0 0
0.5
1
1.5
2
2.5 V 3
V
V
MCD05140
Figure 21
Pull-Up/Pull-Down Characteristics of Class B Pins
Note: The pull-up/pull-down characteristics as shown in Figure 20 and Figure 21 are guaranteed by design characterization.
Data Sheet
64
V1.2, 2002-12
TC1765
Preliminary AD Converter Characteristics
VSS = 0 V; TA = -40 C to +125 C;
Parameter Analog supply voltages Analog ground voltage Analog reference voltage Analog reference ground Analog input voltage range Internal ADC clock Power-up calibration time Sample time Symbol min. Limit Values typ. 2.5 5 - - - - - - max. 2.75 5.25 0.1 V V V 2.25 4.5 -0.1 4 Unit Test Conditions
1)
VDDAx SR VDDM
SR
-
1) 1)2)
VSSAx SR VAREFx SR VAGNDx SR VAIN fANA tPUC
CC SR
VDDM + 0.05 V VSSAx + 0.05 V VAREFx
5 3328 x (3 + CON.CPS) x tBC V MHz s
VSSAx 0.05
1)3)
VAGNDx
0.5 -
1)
- -
tS
CC
(3 + CON.CPS) x (CHCONn.STC + 2) x tBC 6 x tBC - -
s s s s s LSB LSB LSB mA mA mA mA mA mA - -
4)
Conversion time
tC
CC
tS + (30 + CON.CPS x 4) x tBC + 2 x tDIV tS + (36 + CON.CPS x 4) x tBC + 2 x tDIV ts + (42 + CON.CPS x 4) x tBC + 2 x tDIV
for 8-bit conv.4) for 10-bit conv.4) for 12-bit conv.4) for 8-bit conv. for 10-bit conv. for 12-bit conv. -
Total unadjusted error
TUE5) CC
- - -
- - - -
1 2 6 +5 0 +5
Overload current6)
IAOV17) CC -2
-2 0
kA = 1.0 x 10-3 kA = 1.0 x 10-4
-
IAOV28) CC -4
-4 0 Overload coupling factor kA
9)
-
+10 0 +10
kA = 1.0 x 10-3 kA = 1.0 x 10-4
see IAOV1 and
CC
-
-
1.0 x 10-3 1.0 x 10-4
IAOV2
Data Sheet
65
V1.2, 2002-12
TC1765
Preliminary AD Converter Characteristics (cont'd)
VSS = 0 V; TA = -40 C to +125 C;
Parameter Input leakage current at analog inputs Input leakage current at VAGND and VAREF Switched cap. at positive reference voltage input Switched cap. at negative reference voltage input Total capacitance at analog voltage input Symbol min. Limit Values typ. - - 15 max. 200 500 20 nA nA pF CC CC - - - Unit Test Conditions 0 V< VIN < VDDA1) 0 V< VIN < VDDA1)
10)
IOZ1 IOZ2
CAREFSW
CC
CAGNDSW
CC
-
15
20
pF
10)
CAINTOT
CC
- - -
12 - -
15 10 0.7
pF pF k
-
11)
Switched cap. at analog CAINSW CC voltage input ON resistance of the transmission gates in the analog voltage path
1) 2)
RAIN
CC
-
Suffix x = 0 refers to ADC0 and suffix x = 1 refers to ADC1. The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. Definitions for CPS, STC, tBC and tDIV see Figure 23. TUE is tested at VAREF = 5 V, VAGND = 0 V and VDDM = 4.9 V. Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the specified operating range (i.e. VAOV > VDDM + 0.5 V or VAOV < VSSM - 0.5 V) or a short circuit condition occurs on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any time. The supply voltage (VDD, VDDA0, VDDA1 and VSS, VSSA0, VSSA1) must remain within the specified limits. Under short-circuit conditions the corresponding pin is not ready for use. Applies for one analog input pin. Applies for two numeric adjacent analog input pins.
3)
4) 5) 6)
7) 8)
Data Sheet
66
V1.2, 2002-12
TC1765
Preliminary
9)
The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage current (Ileak) into an adjacent pin: |Ileak| = kA x |IOV|. Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN x |Ileak|. See also section 7.1.6 "Error Through Overload Conditions" in the TC1765 Peripheral Units User's Manual for further explanations. This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively, the redistributed charge could be specified. The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively, the redistributed charge could be specified.
10)
11)
R A IN , S o u rce
R A IN , O n
A /D C o nv erte r
V A IN
=
C A IN , B lo ck
C A IN T O T - C A IN S W
C A IN S W
M C S 04879
Figure 22
Equivalent Circuitry of Analog Input
Note: This equivalent circuitry for an analog input is also valid for the reference inputs VAREF and VAGND.
Data Sheet
67
V1.2, 2002-12
TC1765
Preliminary
A/D Converter Module Peripheral Clock Divider (1:1) to (1:8)
fADC
fDIV
Programmable Clock Divider (1:1) to (1:128)
fBC
4:1 3:1
fANA
Programmable Counter
Sample Time tS
CON.PCD Arbiter (1:20)
CON.CTC
CON.CPS
CHCONn.STC
fTIMER
Control Unit (Timer)
Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic
MCA04657
Figure 23
ADC Clock Circuit
Note: The frequency of fADC is the system clock frequency (fSYS) divided by the value of bit field ADCx_CLC.RMC. Oscillator Pins (Class C Pins)
TA = -40 C to +125 C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
Parameter Input low voltage at XTAL1 Input high voltage at XTAL1 Symbol min. Limit values max. 0.3 x V V - - 0 V < VIN < VDDOSC 0 V < VIN < VDDOSC Unit Test Conditions
VILX SR -0.5
VIHX RR 0.7 x VDDOSC Input current at XTAL1 IIX1 CC - Input leakage current IOZ CC -
XTAL1
1)
VDDOSC VDDOSC
+ 0.5
20 200
A
nA
1)
Only applicable in deep sleep mode.
Data Sheet
68
V1.2, 2002-12
TC1765
Preliminary Power Supply Current
TA = -40 C to +125 C;
Parameter Symbol CC - - - - - - - Limit Values min. typ.1) max. Active mode supply current IDD - 260 7 201 31 214) 0.1 123 50 5 1 1 1 200 290 10 - - - - - 900 4.4 250 200 mA mA mA mA mA mA mA mA PORST = VIL2)3) Sum of IDDS4)3) Unit Test Conditions
IDD at VDDP4) IDD at VDD
(Core and EBU)4) 1205) mA
IID Sleep mode supply current ISL Deep sleep mode supply IDS
Idle mode supply current current Stand-by pin power supply ISB current
1) 2)
CC - CC - CC - - CC - -
A
mA
A A
IDD at VDDRAM4) IDD at VDDSBRAM IDD at VDDAx4) PORST = VIH2)6)7) PORST = VIH2)7) PORST = VIH8) PORST = VIH9) IDD at VDDSBRAM10)
11)
Parameters in this column are tested at 25 C, 40 MHz system clock (if applicable) and nominal VDD voltages. These parameters are tested at VDDmax and 40 MHz system clock (bypass mode) with all outputs disconnected and all inputs at VIL or VIH. These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP + VDDRAM + VDDSBRAM + VDDOSC + VDDM + VDDA0 + VDDA1 These power consumption characteristics are measured while running a typical application pattern. The power consumption of modules can increase or decrease using other application programs. The PLL is inactive during this measurement. This parameter has been evaluated at design characterization using an atypical test pattern that makes extensive usage of the DMU memory. All peripherals are enabled and in idle state. Guaranteed by design characterization. This is the sum of all 2.5 V power supply currents. This is the sum of all 5 V power supply currents. TC1765 in deep sleep mode. All other VDD pins are at 0 V; TJ = 150 C; VDDSBRAM = 2.0 V.
3)
4)
5)
6) 7) 8) 9) 10) 11)
Data Sheet
69
V1.2, 2002-12
TC1765
Preliminary AC Characteristics Output Rise/Fall Times Class A drivers (GPIO Ports 0 to 5): VDDP = 3.0 to 5.25 V; VSS = 0 V Class B drivers (Bus interface): VDD = 2.30 to 2.75 V; VSS = 0 V
TA = -40 C to +125 C, unless otherwise noted; fSYS = 40 MHz
Parameter Symbol Limit Values min. typ. Class A Pins Nominal output rise/ fall time1) max. Unit Test Conditions
tRFAnom
CC
-
5
-
ns
TA = 25 C, CL = 50 pF, VDDP = 5.0 V
Px_POCON.PDCy = 0 Px_POCON.PECy = 0
Maximal output rise/ fall time1) Slow output rise/fall time1)
tRFAmax
CC
-
-
12
ns
CL = 50 pF
Px_POCON.PDCy = 0 Px_POCON.PECy = 0
tRFAslow
CC
-
-
55
ns
CL = 100 pF
Px_POCON.PDCy = 0 Px_POCON.PECy = 1
Class B Pins Output rise/fall time1) tRFBmax CC - - - - 4 7 ns ns for ECOUT CL = 50 pF for all Class B pins except ECOUT CL = 50 pF
1)
Measured from 10% output level to 90% output level and vice versa.
Data Sheet
70
V1.2, 2002-12
TC1765
Preliminary Testing Waveforms
TA = -40 C to +125 C; Frequency: max. 40 MHz; Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V;
VIHmin
VOHmin
Test Points
VOHmin VOLmax
MCT04880
VILmax
VOLmax
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0. Input and Output Low/High max./min. voltages are defined at Page 60.
Figure 24
Testing Waveforms for Class A Pins
Class B and Class C Pins: VDD = 2.30 to 2.75 V; VSS = 0 V; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
VIHmin VDD / 2 VILmax
Test Points
VDD / 2
MCT04881
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VDD/2 for a logic 1 and for a logic 0. Input Low/High max./min. voltages are defined at Page 61 and Page 68.
Figure 25
Testing Waveforms for Class B and Class C Pins
VLoad + 0.1 V VLoad - 0.1 V
Timing Reference Points
VOH - 0.1 V VOL - 0.1 V
MCT05074
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 15 mA).
Figure 26
Data Sheet
Tri-State Testing Waveforms for Class B Pins
71 V1.2, 2002-12
TC1765
Preliminary Input Clock Timing
VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; TA = -40 C to +125 C;
Parameter Oscillator clock frequency Symbol direct drive fOSC SR (= 1/tOSC) with PLL 4 10 - 10 7 7 - - Limit Values min. max. 16 16 40 30 - - 4 4 MHz MHz MHz MHz ns ns ns ns Unit
Input clock frequency driving direct drive 1/tOSCDD SR at XTAL1 with PLL Input clock high time Input clock low time Input clock rise time Input clock fall time
t1 t2 t3 t4
SR SR SR SR
t O SC
Inp u t C lo ck a t X TA L1 0 .5 V D D O S C
t1
t2
t4
t3
V IH X V IL X
M C T 04882
Figure 27
Input Clock Timing
Data Sheet
72
V1.2, 2002-12
TC1765
Preliminary ECOUT and CPUCLK Timing
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Clock period Symbol min. Limit Values typ. - max. - ns 25 Unit
tCPUCLK tECOUT
CC
Clock high time Clock low time Clock rise time Clock fall time Clock duty cycle t5/(t5 + t6)
t5 t6 t7 t8 DC
CC CC CC CC CC
7.5 7.5 - - 45
- - - - 50
- - 4 4 55
ns ns ns ns %
tCLKOUT
ECOUT 0.5 VDDP05 CPUCLK
t5
t6
t8
t7
0.9 VDD 0.1 VDD
MCT05228
Figure 28
ECOUT/CPUCLK Output Clock Timing
Data Sheet
73
V1.2, 2002-12
TC1765
Preliminary PLL Parameters Note: All PLL characteristics defined on this and the next page are guaranteed by design characterization.
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C;
Parameter Accumulated jitter VCO frequency range PLL base frequency PLL lock-in time Phase Locked Loop Operation When PLL operation is enabled and configured (see Figure 16 and Page 51), the PLL clock fVCO (and with it the system clock fSYS) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO = K x fSYS. The PLL causes a jitter of fSYS and CPUCLK/ECOUT, which is directly derived from fSYS and which has its frequency. The following two formulas define the (absolute) approximate maximum value of jitter DN in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the number P of consecutive fSYS periods. 23.5 Symbol Limit Values min. max. - MHz MHz 200 130 200 see Figure 29 150 40 - Unit
DN fVCO fPLLBASE tL
s
for P <
K
23.5
DN [ns] =
3.9 x P + 1.2 fSYS [MHz] 91.7
[1]
for P >
K
DN [ns] =
fSYS [MHz] x K
+ 1.2
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower system clock frequency fSYS results in a higher maximum jitter. Figure 29 gives an example for typical jitter curves with K = 4 @40 MHz, K = 6 @33 MHz, and K = 8@20/25 MHz.
Data Sheet
74
V1.2, 2002-12
TC1765
Preliminary
2 .0 ns DN 1 .8 fSYS fSYS fSYS fSYS = = = = 20 25 33 40 MHz MHz MHz MHz (K (K (K (K = = = = 8) 8) 6) 4)
M C D 05141_m od
1 .6
1 .4
1 .2
1 .0
0 1 2 3 4 5 6 7 D N = M a x. jitte r P = N u m b e r o f co n se cu tive f S Y S p e rio d s K = K -d ivid e r o f P L L
P
Figure 29
Approximated Maximum Accumulated PLL Jitter for Typical System Clock Frequencies fSYS
Note: For safe clock generation and PLL operation the definitions and restrictions as defined at pages 50, 51, and 72 must be regarded.
Data Sheet
75
V1.2, 2002-12
TC1765
Preliminary EBU Demultiplexed Timing
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from ECOUT Output delay from ECOUT Data setup to ECOUT Data hold from ECOUT Data valid after ECOUT Data setup to ECIN Data hold from ECIN
1) 2)
Symbol min.
Limit Values max. 9 4 - - -
Unit ns ns ns ns ns ns ns
1) 1)
2) 2)
t10 t11 t12 t13 t15 t31 t32
CC 0 CC -2 SR SR SR SR 9 1
CC 2
see Page 80 - see Page 80 -
Valid for EBU_BUSCONx.26 = 0. Valid for EBU_BUSCONx.26 = 1 (early sample feature).
Data Sheet
76
V1.2, 2002-12
TC1765
Preliminary
ECOUT
ECIN A[23:0] CODE SVM
t10
Address Valid
t11
ADV
t11
t10
CSx
t10
t11
RD
t11
RD/WR
t13 t12
D[31:0] Normal Sampling D[31:0] Early Sampling BC[3:0]
MCT05229
Data Valid
t31 t10 t11
t32
Data Valid
t11
t10
Figure 30
EBU Demultiplexed Read Timing
Note: WAIT timing see Figure 32.
Data Sheet
77
V1.2, 2002-12
TC1765
Preliminary
ECOUT A[23:0] CODE 1) SVM
t10
Address Valid
t11
ADV
t11
t10
CSx
t10
RD
t11
RD/WR
t11
t10
D[31:0] Data Valid
t15
t10
BC[3:0]
1)
t11
t11
t10
CODE remains at high level during a demultiplexed write cycle
MCT05230
Figure 31
EBU Demultiplexed Write Timing
Data Sheet
78
V1.2, 2002-12
TC1765
Preliminary WAIT Timing (FPI Bus to External Memory)
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter WAIT setup to ECOUT WAIT hold from ECOUT WAIT setup to ECOUT WAIT hold from ECOUT
1)
Symbol min.
Limit Values max. - - - -
Unit ns ns ns ns
t50 t51 t52 t53
SR 141) SR 141) SR 11 SR 2
Guaranteed by design characterization.
Synchronous Mode ECOUT
t51 t50
WAIT
t51 t50
Asynchronous Mode ECOUT
t53 t52
WAIT
t53 t52
MCT05231
Figure 32
WAIT Timing (from FPI Bus to external Memory)
Data Sheet
79
V1.2, 2002-12
TC1765
Preliminary EBU Burst Mode Timing
VSS = 0 V, VDD = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from ECIN Data setup to ECIN Data hold from ECIN
1)
Symbol min.
Limit Values max. 14 - -
Unit ns ns ns
t30 t31 t32
CC 2 SR SR 41) 11)
Guaranteed by design characterization.
ECIN
t30
A[23:2] Address Valid
t30
ADV
t30
t30
CS0 CODE
t30
t30
RD
t30
t30
BAA
t30
t31 t32
D[31:0] Note: WAIT must be 1 during a Burst Mode Read Cycle. Valid
t31 t32
Valid
MCT05232
Figure 33
Burst Mode Timing (Instruction Read)
Data Sheet
80
V1.2, 2002-12
TC1765
Preliminary Trace Port Timing (TC1765T only) This timing is applicable for TP[15:0] when CPU or DMA trace mode is enabled (SCU_CON.ETEN = 1).
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter TP[15:0] and BRKOUT high/low from CPUCLK Symbol min. Limit Values max. 8 ns Unit
t55
CC 0
CPUCLK
t55
TP[15:0] BRKOUT Old State New State
MCT05233
Figure 34
Trace Port Timing
Data Sheet
81
V1.2, 2002-12
TC1765
Preliminary SSC Master Mode Timing
VSS = 0 V; VDDP = 4.5 to 5.25 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter SCLK / MTSR low/high from ECOUT MRST setup to SLCK rising/falling edge MRST hold from SLCK rising/falling edge
1)
Symbol min.
1)
Limit Values max. 7 - -
Unit ns ns ns
t60 t61 t62
CC - SR SR 182) 102)
This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines. Guaranteed by design characterization.
2)
tECOUT
ECOUT
t60
SCLK MTSR State n-1
t60
t60
State n
State n+1
t61 t62
MRST
Data Valid
MCT05234
Note: The timing diagram assumes the highest possible baudrate operation. (fSSC = fECOUT, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000H)
Figure 35
SSC Master Mode Timing
Data Sheet
82
V1.2, 2002-12
TC1765
Preliminary Package Outlines P-LBGA-260-2 Plastic Low Profile Pitch Ball Grid Array
GPA09421
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 83 Dimensions in mm V1.2, 2002-12
http://www.infineon.com
Published by Infineon Technologies AG

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